Analytical potential model of raised source drain double gate junctionless field effect transistors

Abstract

A 2D potential model is presented for a raised source drain double-gated junctionless field-effect transistor (RSD DG JLFET). The proposed raised source drain structure features a channel thickness that is smaller than the thickness of the source and drain regions.  The potential model is derived by solving Poisson’s equation, with separate solutions obtained for different regions. Initially, a parabolic potential profile is assumed to extend throughout the entire body. However, since the device comprises alternating depleted and non-depleted regions, the potential profile will not remain uniform across the entire channel. The boundary conditions are derived from the initial assumption, while the solutions to Poisson’s equation vary across different regions. The developed model is compared with simulation results from TCAD and shows an excellent agreement with the TCAD simulation results.