Impact of Nanowire Radius and Channel Thickness with High-k Gate Dielectric in GAA-JLT

Abstract

As the transistor’s size becomes smaller, degradation in the short-channel effects (SCEs) becomes more apparent. This leads to research work on multi-gate transistors such as the Fin-Field Effect Transistor (FinFET) and Gate-All-Around (GAA) transistor, where the 3D architecture have been shown to have superior performance as compared to conventional planar transistor. Transistor without junctions (JLT) which realizes a single type of doping has also been gaining popularity for biosensor applications due to its superior electrostatic performances in terms of Drain-Induced Barrier Lowering (DIBL), off-state leakage current (Ioff) and Subthreshold Slope (SS). In this work, the impact of changes in parameters such as the gate oxide material, nanowire radius and channel thickness toward the performance of a Gate-all-around JLT (GAA-JLT) have been studied using TCAD simulator. It was found that smaller nanowire radius and thicker channel produces lower DIBL, Ioff and SS, with the use of HfO2 as gate oxide materials shows better results than Si3N4. Meanwhile, the impact of parameters variations seemed to be negligible on the on-state current (Ion). The outcome of this work can be used as a basis to understand the impact of structural parameters variations towards the performance of a more complex GAA-JLT structure.