Design and performance analysis of ALU architectures based on quantum-dot cellular automata

Abstract

Quantum-dot cellular automata (QCA) nanotechnology addresses the limitations of Short-Channel Effects (SCE) in metal-oxide-semiconductor field-effect transistors (MOSFETs) at the ultra-nanoscale. The area required for QCA-based circuits is significantly less than that for MOSFET circuits because logic formation relies entirely on electron flow. QCA nanotechnology offers high speed and reduced energy dissipation. The arithmetic and logical unit (ALU) is a key component of a processor. Therefore, this paper evaluates various ALU designs in QCA nanotechnology and provides a competitive analysis. The different quantitative measurements are considered for comparison purposes. The literature offers various multi-layer implementations of ALUs. There is a need for an efficient design of a single-layer ALU in QCA nanotechnology that utilizes a minimal number of QCA cells and clocking phases. An ALU design without any crossing mechanism and a multi-layer configuration consists of only 57 QCA cells and has a 0.75 clock delay. Compared to existing designs, the proposed ALU achieves up to 94% reduction in QCA cell count, 97% reduction in layout area, and nearly 99.6% improvement in area-delay product, based on worst-case values from previously reported designs. A comparative evaluation against multiple benchmarks demonstrates superior area, delay, and functional output performance. These findings underscore the proposed ALU's potential for scalable, low-power QCA-based processors.