Improvement of gate oxide thickness uniformity in advanced U-MOSFETs through multi-layer furnace oxidation

Abstract

Gate oxide uniformity is very important to the electrical wafer test performance such as Breakdown Voltage (B_VDSS), Gate Source Leakage Current (I_GSS), Gate Charge and reliability for vertical trench MOSFETs (U-MOSFETs), particularly in advanced scaling designs with compact cell layouts for lower Drain Source On Resistance (R_DSON). This study investigates gate oxide formation in a high-density N-type 30V UMOSFET with a 0.8 µm cell pitch from Product B. Conventional dry oxidation produces non-uniform oxide thickness, especially at the trench corners, leading to degradation of the B_VDSS and leakage characteristics (I_GSS). To address this, we propose a multi-layer thermal oxidation process combining the dry and wet oxidation, achieving improved corner coverage while maintaining a target gate oxide thickness of 500 Å. Transmission electron microscopy (TEM) analysis confirms that the multi-layer thermal oxidation (dry and wet oxidation) method reduces thickness variation from more than 25% to less than 10% compared to pure dry oxidation. Electrical characterization shows enhanced B_VDSS, I_GSS and stable threshold voltage (V_TH) without impacting (R_DSON). These results demonstrate that the proposed multi-layer thermal oxidation process is an effective approach for fabricating robust gate oxides in next-generation, scaled power MOSFETs. It is suggested that trench depth and P-body doping are further optimized to improve the balance between breakdown voltage and threshold voltage.