Evaluate the impact of advanced cell pitch on U-MOSFET wafer edge IGSS failure in a CMOS environment

Abstract

Power MOSFET remains a key device platform in the semiconductor market demand, and this has drawn attention to SilTerra in the long-term supply chain, which provides additional manufacturing loading. In this work, the evaluation of the advanced cell pitch of a vertical trench MOSFET or U-MOSFET was selected due to its process compatibility in a CMOS fabrication environment. A major challenge was identified during the product ramping stage, exhibiting inconsistency for gate-to-source leakage (IGSS) on the wafer edge across different production lots, along with trench Final Inspection Critical Dimension (FICD) and threshold voltage (VTH) variation. Failure analysis revealed that affected IGSS failure wafers have shown a wider trench critical dimension (CD) and misalignment between the contact and trench on the wafer edge. Inline containment activities were implemented on precise process control for trench final inspection critical dimension (FICD) and tighter alignment measurement in order to achieve stable IGSS; however, this stringent inline process control has increased the rework rate. With the systematic trench mask development inspection critical dimension (DICD) split, it is confirmed that wider trench spacing or CD increases IGSS failure at the wafer edge and overall VTH variation; the optimal trench FICD control target is identified at 200 nm +/- 12 nm for stable IGSS performance, and it is observed that CD bias between DICD and FICD is not at zero. To address the alignment mark issues, the layout structure was evaluated using technology computer-aided design (TCAD) simulation and tape-out for the experiment. The result of the new alignment has demonstrated a better process margin with the lowest IGSS failure.