Design and Electrical Simulation of a 22nm MOSFET with Graphene Bilayer Channel using Double High-ĸ Metal Gate

Abstract

This paper will discuss the virtual fabrication design process of a 22nm MOSFET bilayer graphene with high-ĸ metal gate (HKMG). Silvaco software's TCAD fabrication tools were utilized, with the Athena simulation module used to construct the device design and the Atlas module used to describe the device's electrical characteristics. To get the electrical characterization of a transistor specified by international standards, fixed field scaling methods were employed. Advanced and new methods were used to reduce the problems that occur during the manufacture of nano-sized transistors while increasing their performance. The material is Titanium dioxide (TiO2), while the metal gate is Tungsten Silicide (WSiX). The simulated devices conform to the International Technology Roadmap Semiconductor (ITRS) specifications. The results show that Vth is 0.206 ± 12.7% V for high performance (HP) logic technology requirements.