A novel technique for designing ternary logic arithmetic circuits using GNRFETs to enhance energy efficiency and circuit performance

Abstract

Ternary logic systems provide many benefits over typical binary logic, including faster logic and arithmetic operations, lower connection complexity, and a smaller footprint. This study describes ternary logic circuit designs. A novel design strategy is presented for developing ternary logic circuits using graphene nanoribbon field-effect transistors (GNRFETs). The GNR dimer line controls the GNRFET's threshold voltage and width. Designs such as half adder and multiplier circuits are presented using fewer transistors. The adder and multiplier schematics are created utilizing a variety of ternary unary operators. The Synopsys HSPICE tool is used to build and simulate the proposed circuitry. The proposed designs' performance parameters, including delay, power dissipation, and power delay product (PDP), are studied and compared with typical CNTFET circuits. The proposed schematics enhanced overall performance by up to 42.12% over CNTFET devices. Furthermore, the PDP of the proposed designs is compared to previous literature. The suggested circuits enhance the PDP by up to 69.64% compared to the current works. In addition, the effect of process, voltage, and temperature (PVT) variations on the proposed adder and multiplier designs is examined. It was discovered that adder and multiplier circuits exhibited the fewest differences in performance for PVT fluctuations. The ternary full adder circuit is then developed as a complex circuit and compared to a CNTFET-based circuit to determine its performance