Investigation on Geometrical Effects of FinFET Electronic Device Properties Using TCAD Simulations and Taguchi Optimization

Abstract

Accurate determination of transistor size parameters is necessary to provide ideal operating conditions and performance. Using Design of Experiments (DoE) techniques to enhance device performance and efficiency, this work explores the Taguchi strategy for optimizing device parameters in a 7 nm Silicon FinFET. This study examines how geometric scaling influences FinFET performance, focusing on the ratio of on-state current (ION) to off-state current (IOFF), threshold voltage (VTH), subthreshold swing (SS), and drain-induced barrier lowering (DIBL). The Taguchi method is used to improve the FinFET model, leading to better performance. In addition, the study of the impact of improved FinFETs on the performance of logic circuits, especially regarding delay and power requirements. Silvaco TCAD Simulator is used in this work for simulation and analysis. The Taguchi method was used to identify the optimal factor combination for robust device performance, with orthogonal arrays and Signal-to-Noise Ratio (SNR) as the selected quality parameter. The parameters considered in the Design of Experiments (DoE) include Length (LG), Fin Height (HFIN), and Fin Width (WFIN) in the top region. The parameters for the ION/IOFF ratio, VTH, DIBL, and SS were identified using Taguchi’s robust performance signal-to-noise ratio (SNR). The VTH value is 0.7461V for the FinFET, with LG, WFIN, and HFIN ranging 13 nm, 7 nm, and 35 nm, respectively. FinFET yielded a current ratio of 262.072 and SS of 72 mV/dec when LG was 13 nm, WFIN was 5 nm, and HFIN was 40 nm. When the FinFET has LG, WFIN, and HFIN of 10 nm, 10 nm, and 35 nm, respectively, it produces the optimum DIBL of 232 mV/V. Overall, the analysis demonstrates that FinFET performance can be substantially enhanced by dimension optimization. Additionally, the Taguchi approach effectively identified the optimal parameter combinations, which were then employed in logic circuits to create low-power FinFETs.