Performance evaluation of novel mid-insulation gate junctionless transistors at the device and circuit level

Authors

  • Sonali Keithellakpam North Eastern Hill University (A Central University), Shillong-793022, India
  • Papu Doley North Eastern Hill University (A Central University), Shillong-793022, India
  • Nipanka Bora North Eastern Hill University (A Central University), Shillong-793022, India

Keywords:

Mid-insulation gate, Junctionless transistor, Surface potential, Drain current, Transconductance

Abstract

This work proposes a novel gate-engineered Mid-Insulation Gate Junctionless Transistor (MiG-JLT) and presents a comparative per

This work proposes a novel gate-engineered Mid-Insulation Gate Junctionless Transistor (MiG-JLT) and presents a comparative performance evaluation against the conventional Symmetric Double Gate Junctionless Transistor (SDG-JLT). Under identical physical parameters, the proposed MiG-JLT demonstrates a nearly 35% enhancement in ON-state current, achieving an ON current of approximately 2.5  10–5 A and an ION/IOFF ratio of about 2.5  108. For a silicon body thickness of 10 nm, the device exhibits a peak transconductance of ~7  10–5 S, and a drain conductance of ~1.3  10–4 S at low drain bias, confirming its improved analog performance. The effects of doping concentration, surface potential distribution, and channel width are systematically analyzed. Circuit-level inverter analysis further demonstrates enhanced transfer and switching characteristics. Overall, the proposed MiG-JLT shows strong potential for high-performance nanoscale and SPICE-compatible device applications.

formance evaluation against the conventional Symmetric Double Gate Junctionless Transistor (SDG-JLT). Under identical physical parameters, the proposed MiG-JLT demonstrates a nearly 35% enhancement in ON-state current, achieving an ON current of approximately 2.5  10–5 A and an ION/IOFF ratio of about 2.5  108. For a silicon body thickness of 10 nm, the device exhibits a peak transconductance of ~7  10–5 S, and a drain conductance of ~1.3  10–4 S at low drain bias, confirming its improved analog performance. The effects of doping concentration, surface potential distribution, and channel width are systematically analyzed. Circuit-level inverter analysis further demonstrates enhanced transfer and switching characteristics. Overall, the proposed MiG-JLT shows strong potential for high-performance nanoscale and SPICE-compatible device applications.

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Published

29-04-2026

How to Cite

[1]
Sonali Keithellakpam, Papu Doley, and Nipanka Bora, “Performance evaluation of novel mid-insulation gate junctionless transistors at the device and circuit level”, IJNeaM, vol. 19, no. 2, pp. 349–355, Apr. 2026.

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