Electrical Performance Evaluation Based on Design Parameters of Silicon Nanowire Gate-All-Around (GAA) TFET

Abstract

The silicon nanowire gate-all-around (SiNW GAA) is one of the technologies with potential for improved short-channel behavior and gate control over conductivity. This work investigates the impact of various geometrical sizes on the electrical properties of SiNW GAA tunneling field-effect transistor (TFET). The gate oxide thickness (TOX), channel radius, type of dielectric, gate metal work function, with low or high drain voltage are varied to analyze the electrical characteristics of SiNW GAA TFET. The electrical characteristics studied in this work consist of subthreshold slope (SS), current ratio, and threshold voltage (Vth). The findings indicate that an oxide thickness of 3 nm, a channel radius ranging from 10 nm to 18 nm, and the use of SiO2 as a dielectric material are optimal for achieving superior characteristics in SiNW GAA TFETs.. The gate metal TiN exhibits a work function that, in conjunction with a drain voltage of 0.5 V, optimally enhances device performance. This study highlights the potential of GAA nanowire TFETs to drive innovation in semiconductor technology through superior electrical performance.